CD4027 - Dual J-K Master/Slave Flip-Flop with Set and Reset

The CD4027BC dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. Each flip-flop has independent J, K, set, reset, and clock inputs and buffered Q and Q outputs. These flip-flops are edge sensitive to the clock input and change state on the positive-going transition of the clock pulses. Set or reset is independent of the clock and is accomplished by a high level on the respective input. All inputs are protected against damage due to static discharge by diode clamps to V_DD and V_SS.

Features

• Wide supply voltage range: 3.0V to 15V
• High noise immunity: 0.45 V_DD (typ.)
• Low power TTL compatibility: Fan out of 2 driving 74L or 1 driving 74LS
• Low power: 50 nW (typ.)
• Medium speed operation: 12 MHz (typ.) with 10V supply
• This is a Thru-Hole Device

Data Sheet